Author

Date of Award

8-20-2013

Document Type

Thesis

Degree Name

Master of Science (MS)

Department

Applied Science

First Advisor

Kenji Yoshigoe

Abstract

Achieving low power consumption, size reduction, and space optimization are all challenges in resource constrained wireless devices such as Wireless Sensor Network (WSN) nodes. WSN nodes use duty cycle to improve their power efficiency, and wake-up radio (WUR) is used as a control channel to wake them up. A field-programmable gate array (FPGA) is one of the attractive candidates for WSN devices implementation. A low-profile WUR scheme is proposed and implemented using FPGA to address the challenge of power consumption for resource-constrained wireless devices. First, a new design to partition WUR from the remaining main radio component and data processing module using a chipset with flash-freeze technology is proposed and implemented. Second, a WUR mechanism for unicast, broadcast, and pseudo multicast communication with a minimal amount of register is proposed and implemented. An elimination of unnecessary power consumption results in significant cumulative power reduction for resource-constrained wireless devices with a range of direct neighbor nodes.

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